FPGA developer in Sili Oboroni

Overview

The vacancy involves service in the technical unit of the Defense Forces. The candidate will be responsible for the development and maintenance of SDR-based wireless communication projects.

Responsibilities

• creation and development of IP-core and projects for FPGA series Xilinx Zynq and Atlera (Intel) Cyclone FPGA
• transfer of current algorithms from C/C++ in FPGA
• implementation of CSO algorithms from Matlab in FPGA
• development of new CSO algorithms
• writing tests (testbench) for verification and simulation < /li>
• testing and debugging of projects on "iron"
• creation of technical documentation

Requirements

• programming experience on in Verilog/VHDL/SystemVerilog languages ​​from 5 years
• project management experience from 2 years
• experience in Vivado IDE environment
• experience in Quartus Prime environment
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• experience working with measuring equipment
• knowledge of analog and digital circuitry
• knowledge of digital signal processing algorithms
• understanding of programs written in high-level languages ​​( C/C++, MATLAB)
• higher education in electronics and telecommunications, computer science (candidates with education in related fields will also be considered)

Conditions

• contract service until the end of martial law
• stable financial support in accordance with the norms of current legislation
• rank of rank and file